Discover Unknown PCB Design Issues with HyperLynx DRC

Overview:

This paper addresses several of the pervasive myths within the PCB verification market, such as the need for post-layout PCB verification on high-speed designs only. Additionally, it discusses how a designer can seamlessly integrate with the PCB design process to find issues that are often missed by current PCB verification methods.

An Introduction to HyperLynx SI/PI Technology

Overview:

Are you working with new methodologies like COM (channel operating margins), PAM4 (pulse amplitude modulation with 4 states), and HMC (hybrid memory cube & other 3D memory architectures)? HyperLynx® SI/PI tackles those challenges in a single unified environment that includes integrated signal- and power-integrity analysis, 3D-electromagnetic solving, and fast DRC checking. Design any type of high-speed digital
PCB with HyperLynx.

How Formal Reduces Fault Analysis for ISO 26262

Overview:

The ISO 26262 standard defines straightforward metrics for evaluating the “safeness” of a design by defining safety goals, safety mechanisms, and fault metrics. However, determining those metrics is difficult. Unlike simulation where it is never known if the design has been simulated enough or given enough input, formal verification conclusively determines if faults are safe or not, making the failure rates from formal analysis more than an arbitrary number determined by fault simulation. Formal analysis tools that apply SLEC techniques are an ideal solution for fault pruning, fault analysis, and determining diagnostic coverage. This paper discusses how to use formal verification for static and transient fault analysis to generate ISO 26262 safety metrics, first describing fault pruning and then the more sophisticated fault injection using SLEC.

UVM: The Next Generation in Verification Methodology

Overview:

UVM is a new verification methodology that was developed by the verification community for the verification community. UVM represents the latest advancements in verification technology and is designed to enable creation of robust, reusable, interoperable verification IP and testbench components.