7 Design Aspects of IoT PCB Designs
To consumers, IoT devices look sleek and simple, but they are comprised of a distinct set of components, physical interfaces, PCBs, and circuitry that presents unique design and layout challenges. This paper looks at seven things to consider when designing PCBs for successful IoT devices.
How Small PCB Design Teams Can Solve High-Speed Design Challenges with Design Rule Checking
Coping with SI (signal integrity) and EMI (electromagnetic interfaces) issues is a daily challenge for PCB design engineers and small teams. Avoid end-product problems such as emissions testing failures or signal-integrity-related failures by using design rule checks (DRCs). This paper reviews the common causes of SI/EMI challenges and how they can be easily identified.
Ten Things to Know about Thermal Design of Electronic Products
How should engineers who develop products with complex and/or high-power electronics ensure the thermal performance of their products while meeting other design criteria?
To answer this question, this paper will take a look at ten things you should know about thermal design of electronic products.
Frontloading CFD – Required Technologies
Today manufacturing product design cycles need to get shorter and shorter as either new or increased numbers of products get to the market faster. In the automotive industry for example, with either facelifts to existing car models, or the next generation of the model appearing almost every 3-4 years, and an increasing number of new models appearing on the market, the demand on engineering design centers is to produce the same or higher quality products in a shorter time.
Top 7 Tips to Increase Engineering Productivity by Frontloading CFD
The global competitive landscape for manufacturing is squeezing everyone—from the Tier 1 automotive companies to electronics goods manufacturers. It is shortening the required time to market and with little warning. This high-pressure environment requires high productivity from its players resulting in either doing things faster and leaner without compromising quality or giving the game away to a hungrier competitor who is willing to do whatever it takes. So how do you become more productive? Read this whitepaper to learn 7 tips that can be implemented immediately to help you increase productivity today.
Discover Unknown PCB Design Issues with HyperLynx DRC
This paper addresses several of the pervasive myths within the PCB verification market, such as the need for post-layout PCB verification on high-speed designs only. Additionally, it discusses how a designer can seamlessly integrate with the PCB design process to find issues that are often missed by current PCB verification methods.
An Introduction to HyperLynx SI/PI Technology
Are you working with new methodologies like COM (channel operating margins), PAM4 (pulse amplitude modulation with 4 states), and HMC (hybrid memory cube & other 3D memory architectures)? HyperLynx® SI/PI tackles those challenges in a single unified environment that includes integrated signal- and power-integrity analysis, 3D-electromagnetic solving, and fast DRC checking. Design any type of high-speed digital PCB with HyperLynx.
How Formal Reduces Fault Analysis for ISO 26262
The ISO 26262 standard defines straightforward metrics for evaluating the “safeness” of a design by defining safety goals, safety mechanisms, and fault metrics. However, determining those metrics is difficult. Unlike simulation where it is never known if the design has been simulated enough or given enough input, formal verification conclusively determines if faults are safe or not, making the failure rates from formal analysis more than an arbitrary number determined by fault simulation. Formal analysis tools that apply SLEC techniques are an ideal solution for fault pruning, fault analysis, and determining diagnostic coverage. This paper discusses how to use formal verification for static and transient fault analysis to generate ISO 26262 safety metrics, first describing fault pruning and then the more sophisticated fault injection using SLEC.
UVM: The Next Generation in Verification Methodology
UVM is a new verification methodology that was developed by the verification community for the verification community. UVM represents the latest advancements in verification technology and is designed to enable creation of robust, reusable, interoperable verification IP and testbench components.