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Electronic System Level Design

Vista

A Complete TLM 2.0-based Solution

Today’s advanced designs have become too massive and complex for traditional RTL methodologies. Electronic System Level (ESL) design methodologies address this problem by elevating design and verification to a higher level of abstraction, where many engineering tasks and design optimizations can be successfully accomplished more quickly, more efficiently, and more cheaply than at the RTL.

Vista™ is an integrated TLM 2.0-based solution for architectural design exploration, verification, and virtual prototyping. Vista enables system architects and SoC designers to make viable architecture decisions, and it allows hardware and software engineers to validate their hardware and software early in the design cycle.

This is accomplished by prototyping, debugging, and analyzing complex systems before the RTL stage, establishing a predictable and productive design process that leads to first-pass success.

 

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